As ground rule dimensions shrink in integrated circuits, the problem of filling high aspect ratio trenches increases, in particular for isolation trenches used in shallow trench isolation processes, STI, which is commonly used in advanced processing.
Furthermore, with higher aspect ratios it becomes increasingly difficult to fill trenches with dielectric material free of voids and gaps. A possibility to overcome this problem is to use spin-on dielectric materials in order to fill the trenches. However, spin-on dielectric materials or spin-on glass have to subjected to a densification and/or curing process. The densification process is necessary in order to obtain e.g. a low wet etch rate for further wet etch processes. Unfortunately, the densification process is accompanied by a shrinkage of the material, which is not homogeneous in depth for high aspect ratio trenches. This is caused by the material sticking to the walls of the trenches and strongly depends on the shape of the filled structure. Particularly, for integration schemes for three-dimensional devices chemicals attack the dielectric filler material of the isolation trench whereby the insufficient curing and/or densification results in a high etching rate which is unfavourable.
The proposed invention describes a method which uses a sacrificial material in order to provide a reservoir of the filler material which will be consumed by a subsequent densification process. Additionally, the removal of the sacrificial material prior to the densification ensures a densification process with increased homogeneity.
U.S. Pat. No. 6,869,860 describes a filling of high aspect ratio isolation structures with polysilazane-based materials. In this document, spin-on glass or spin-on dielectric material for filling trenches of semiconductor devices, e.g. shallow trench isolation (STI), is described.
An integrated circuit containing a set of thermally sensitive circuit elements having a thermal budget associated therewith and comprising a set of isolation trenches is processed by means of the following steps: providing a silicon substrate; forming at least one circuit element having a thermal budget prior to forming the isolation structure; etching said set of trenches in said silicon substrate; filling said set of trenches with a spin-on trench dielectric material containing silazane; heating said substrate at a temperature of less than about 450° C. converting the stress in said trench dielectric material from tensile stress to compressive stress by heating in an ambient containing H2O at a temperature between approximately 450° C. and about 900° C.; annealing said substrate by heating in an ambient containing oxygen at a temperature above 800° C.; and completing said integrated circuit. Additionally, the trench dielectric material is planarized by CMP after the step of annealing in an oxygen ambient; and an anneal in an ambient containing water vapour is performed after the step of planarizing for a time sufficient to convert silicon nitrogen bonds to silicon oxygen bonds in trench dielectric material at the bottom of the trench.
Additionally, U.S. Pat. No. 6,699,799 B2 discloses a method for forming a semiconductor device. The method of forming a semiconductor device includes a liner which is conformably stacked on a semiconductor substrate before depositing a spin-on glass layer thereon. Thereafter, the spin-on glass layer is cured, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen or hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultra-violet rays to ozone or forming oxygen plasma. The spin-on glass layer is preferably made of polysilazane-based materials which may promote a conversion of the spin-on glass layer into a silicon oxide layer. During the high temperature annealing process, the silicon layer arranged beneath the spin-on glass layer is converted into a silicon oxide layer by diffused oxygen.